hello so recently i decided to compile a custom over-clocked kernel for the mecha the first modification was to change some of the cpu frequency's but after doing so and compiling when i try to boot with the kernel installed my phone just seems to lock up and never boot. the code seems good to me but i figure ill let you all have a look.
Code:
static struct cpufreq_frequency_table freq_table[] = {
{ 0, 250000 },
{ 1, 350000 },
{ 2, 450000 },
{ 3, 550000 },
{ 4, 650000 },
{ 5, 750000 },
{ 6, 850000 },
{ 7, 950000 },
{ 8, 1050000 },
{ 9, 1150000 },
{ 10, 1250000 },
{ 11, 1350000 },
{ 12, 1450000 },
{ 13, 1550000 },
{ 14, 1650000 },
{ 15, 1750000 },
{ 16, 1850000 },
{ 17, 1950000 },
{ 16, CPUFREQ_TABLE_END },
};
/* Use negative numbers for sources that can't be enabled/disabled */
#define SRC_LPXO (-2)
#define SRC_AXI (-1)
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 24576, SRC_LPXO, 0, 0, 30720, 900, VDD_RAW(900) },
{ 61440, PLL_3, 5, 11, 61440, 900, VDD_RAW(900) },
{ 122880, PLL_3, 5, 5, 61440, 900, VDD_RAW(900) },
{ 184320, PLL_3, 5, 4, 61440, 900, VDD_RAW(900) },
{ MAX_AXI_KHZ, SRC_AXI, 1, 0, 61440, 900, VDD_RAW(900) },
{ 250000, PLL_3, 5, 2, 122500, 900, VDD_RAW(900) },
{ 350000, PLL_3, 5, 1, 192000, 950, VDD_RAW(950) },
{ 450000, PLL_1, 2, 0, 192000, 950, VDD_RAW(950) },
{ 550000, PLL_3, 5, 1, 192000, 975, VDD_RAW(975) },
{ 650000, PLL_2, 3, 0, 192000, 1000, VDD_RAW(1000) },
{ 750000, PLL_2, 3, 0, 192000, 1025, VDD_RAW(1025) },
{ 850000, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 950000, PLL_2, 3, 0, 192000, 1050, VDD_RAW(1050) },
{ 1050000, PLL_2, 3, 0, 192000, 1100, VDD_RAW(1100) },
{ 1150000, PLL_2, 3, 0, 192000, 1150, VDD_RAW(1150) },
{ 1250000, PLL_2, 3, 0, 192000, 1175, VDD_RAW(1175) },
{ 1350000, PLL_2, 3, 0, 192000, 1225, VDD_RAW(1225) },
{ 1450000, PLL_2, 3, 0, 192000, 1300, VDD_RAW(1300) },
{ 1550000, PLL_2, 3, 0, 192000, 1400, VDD_RAW(1400) },
{ 1650000, PLL_2, 3, 0, 192000, 1400, VDD_RAW(1400) },
{ 1750000, PLL_2, 3, 0, 192000, 1450, VDD_RAW(1450) },
{ 1850000, PLL_2, 3, 0, 192000, 1450, VDD_RAW(1450) },
{ 1950000, PLL_2, 3, 0, 192000, 1450, VDD_RAW(1450) },
{ 0 }
};
before I modified this area the kernel booted fine.
the rest of the code is a clone of adrynalyne's master source.
Adryn's new kernel supports changing that information on the fly. Also, why would you want so many frequencies? That would actually make it less effiecent.
I wanted to test certain speeds/voltages on my phone still why won't it boot up the voltages and clock speeds as so.
Sent from my ADR6400L using XDA App
Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
I found the way myself, seems that noone is interested in such topic!
chacona said:
Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
Click to expand...
Click to collapse
chacona said:
Hi all,
I found the way to OC my kernel up. That
Code:
/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};
What we have to do is:
1. Declare a new struct, that is copied from defaults like this:
Code:
struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
2. Initialize: do the following changes (the commented out line is the former, the normal is my change)
Code:
/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;
3. Change static void __init acpu_freq_tbl_fixup(void)
Code:
...
case 0x00:
max_acpu_khz = 1228800;
break;
...
Build it, then you'll done!
My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:
Do you know the relationship between the frequency and loops_per_jiffy?
Recommended VDD value (int vdd) with each value of frequency?
unsigned int sc_core_src_sel_mask;: how do we use it effectively?
For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!
Change list: http://www.mediafire.com/?zc3sg4i912vk681
Click to expand...
Click to collapse
Quite interesting!!!!
What does your kernel do apart from overclocking ?
Does it resolve the voice issue in CM 7?
If any advantages kindly suggest
Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?
chacona said:
Hi, recently I have to work using C#, so I have no time to investigate more on CM7. With CM7, currently I notice that there are issues regarding keys such as MUTE, CAMERA, and kernel power issues. What is the voice problem with CM7, could you tell me?
Click to expand...
Click to collapse
The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine
prasad12ka4 said:
The voice issue is:
Then someone calls and you answer, other person hears a garbeled voice,
But if you disconnect and recall its working fine
Click to expand...
Click to collapse
Okay, thank you for your information. With the information from The Manii about the Phoenix kernel, I am testing their work to see whether problems in stock kernel are solved or not. I will note this issue to see whether I can fix it. At least, I think we should have a good working kernel first.
hope we could make it work, would be cool to have it at least at 1.4 to 1.9 or even 2ghz
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AOSPA 4.3+ PARANOIDANDROID
Kitkat 4.4.2 KVT49L android-4.4.2_r2.1
Download ROMS from DOWNLOAD HERE
1. DOWNLOAD YOUR ROM
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http://goo.gl/mYKmfL - RECOMMEND mini modular PA Gapps
or BANKS - if having issues with PA Gapps
Wipe Fresh Clean Install (you all know the procedure)
3. COMPLETE CLEAN WIPE - *includes system*
4. FLASH ROM & GAPPS
5. WIPE CACHE & DALVIK
5. RUN INITIAL SETUP & REBOOT
Let boot take as much time as needed. This will help avoid boot issues.
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If you're going to post here, keep it to this ROM and this ROM only (unless its fun as mentioned above). It is useless to compare to Stock ROMs, CM10 ROMS, ect...
Please watch the 2 videos provided below before posting in this thread. thanks
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This is an paste from Harsh from his thread here
Well, our cpu are made at some quality standards. We have 4 different quality of cpu for apq8064 from Qualcomm. so depending on which one is on your phone it selects frequency table from slow, nominal, fast and faster.
Google kernel source have same frequency table for fast and faster. So those with faster are not getting their extra advantage
You can identify you CPU chip by below command in terminal.
adb shell dmesg | grep PVS
It will give you some output as given example below
Click to expand...
Click to collapse
Code:
adb shell dmesg | grep PVS
[ 0.873920] acpuclk-8064 acpuclk-8064: ACPU PVS: FAST
And faster binned CPU has lot to do with UV, when you look as frequency table of faster, it is already preconfigured to have lower voltages than fast, and lot lower than slow binned.
Phones with faster binned should have better battery than slower binned phone out of box without any other configuration.
And for UV its already hardcoded and can be adjusted by System Tuner app further. And OC I am not willing to add. ( I don't think there's any gain in running our phones hotter with higher voltages by OC'ing)
Click to expand...
Click to collapse
default voltages for SLOW:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 950000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 975000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 975000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 1000000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 1000000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 1025000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1075000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1075000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1100000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1100000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1125000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1125000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1200000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1200000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1225000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1225000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1237500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1250000 },
default voltages for NORM:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 900000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 925000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 925000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 950000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 950000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 975000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 975000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 1025000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 1025000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1050000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1050000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1075000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1075000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1125000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1125000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1150000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1150000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1175000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1175000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1187500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1200000 },
default voltages for FAST & FASTER:
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(0), 850000 },
{ 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 875000 },
{ 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 875000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 900000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 900000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 },
{ 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(6), 925000 },
{ 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(6), 975000 },
{ 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(6), 975000 },
{ 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(6), 1000000 },
{ 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(6), 1000000 },
{ 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(6), 1025000 },
{ 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(6), 1025000 },
{ 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(15), 1075000 },
{ 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1075000 },
{ 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(15), 1100000 },
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(15), 1100000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(15), 1125000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(15), 1125000 },
{ 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(15), 1137500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(15), 1137500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(15), 1150000 },
So glad to see this here, houstonn! Excellent job my friend.
:good: :highfive:
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Agreed. I'm still rocking the 3/29 build haha
Pie Control works fine for me. It only gave me issues when I flashed the build from 4/2
____
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And here we go! Comm. take off time!:crying:I'm so happy!!!
Wow for a moment I was confused whether I was looking at N4 forums...
Great work Devs! You guys are awesome!
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This is awesome, I'm loving it. Thanks to all the devs involved, great work.
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Curious as to why it will not let me lower min frequency. I lower it but it always puts it right back at 1026....killing my battery.
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Look at cpu spy, I think you will find it actually is going below and just not reporting correctly.
Edit: I just looked at cpu spy and you are in fact correct. Holding steady at 1026+...getting great deep sleep though!
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Jank4AU said:
Look at cpu spy, I think you will find it actually is going below and just not reporting correctly.
Edit: I just looked at cpu spy and you are in fact correct. Holding steady at 1026+...getting great deep sleep though!
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Click to expand...
Click to collapse
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
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pfoxdizzle said:
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
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Click to expand...
Click to collapse
Blame Google. Its called touch boost
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Never heard of this and found nothing on the internet. Would appreciate a pm if you get the chance.
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pfoxdizzle said:
Never heard of this and found nothing on the internet. Would appreciate a pm if you get the chance.
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Click to expand...
Click to collapse
Chad explained it to me. Its built in to boost up the CPU upon touches to prevent lag. Found it in some n4 threads too
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It states that this comes with a modded
Faux kernel. Use fauxclock to disable mpdecision and you'll be able to go below 1GHz. Hopefully the intellidemand governor is present or all 4 cores might be forced online by this.
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pfoxdizzle said:
Deep sleep is good here as well. Seems like it would be amazing if it would allow itself to clock down. Nothing I do will get my settings to persist. Neither in built in performance control or when I tried setcpu.
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Click to expand...
Click to collapse
What governor are you using? After experimenting with it a little, it appears that Conservative is locked to a low of 1026, but the others like Wheatley and OnDemand behave normally...
Jank4AU said:
What governor are you using? After experimenting with it a little, it appears that Conservative is locked to a low of 1026, but the others like Wheatley and OnDemand behave normally...
Click to expand...
Click to collapse
I tried all the governors. Was also sent to the glorious demigod screen after a reboot so reverting back to my CM backup for now.
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Hmm idk about this build, but I'm on the 3/29 build and I'm running the interactive governor clocked to a max of 1512 and min of 288
Deep sleep over night was around 7 hours and 35 minutes out of 7 hours and 38 minutes or something.
blenkows said:
Hmm idk about this build, but I'm on the 3/29 build and I'm running the interactive governor clocked to a max of 1512 and min of 288
Deep sleep over night was around 7 hours and 35 minutes out of 7 hours and 38 minutes or something.
Click to expand...
Click to collapse
It goes down to 288. Just a display bug in apps. The phone scales down.
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nygfan760 said:
It goes down to 288. Just a display bug in apps. The phone scales down.
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Click to expand...
Click to collapse
Edit: I shouldn't be posting here yet. I'm still on the 0404 build and running the 0408 kernel so I don't know if everything is the same kernel-wise. So excuse me while I bow out for a bit until I'm up to date.
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