PDS PARTITION FIX (Screen+Cpu's frenquency restored) [SOLVED] - Atrix 4G Q&A, Help & Troubleshooting

SOLVED
steps are the same to flash pds backup:
choose your version: froyo (*_v4) or gingerbread (*_v8)
METHOD 1 (locked bootloader)
extract the img file
Code:
adb push pdsfix.img /data/local/tmp
adb shell
su
chmod 777 /data/local/tmp/pdsfix.img
dd if=/data/local/tmp/pdsfix.img of=/dev/block/mmcblk0p3
exit
exit
adb reboot
METHOD 2 (UNlocked bootloader)
can use these commands in fastboot mode :
(remember to place the pds.img in the same folder where you have the moto-fastboot executable)
Code:
moto-fastboot flash pds pdsfix.img
moto-fastboot reboot
Enjoy
PS: IN SOME CASES YOU NEED TO WIPE CACHE...
if wiping thru cmw recovery does not help try the following commands to deeply erase thru fastboot
Code:
Fastboot getvar boot-mode
Fastboot erase cache
fastboot reboot
PPS if Method 2 does not work for you, try Method 1...it's universal
BIG THANKS TO eval- for sharing his own files with me!
Found that somehow the mmcblk0p3, the infamous PDS partition si different in the retail phones from the one provided in the devs kit
Edited so you'll have the default wifi and bt mac address assigned in the dev kit
off course you are free to edit yourself again as you wish

---

I have the opposite problem, my cores are running at 1000mhz and 0mhz respectively. I think I need a new gingerbreads. WOr that cool new rom thats optimized for dual corez.
KeRmiT80 said:
the problem is the following:
Code:
Microsoft Windows [Versione 6.1.7601]
Copyright (c) 2009 Microsoft Corporation. Tutti i diritti riservati.
C:\Users\KeRoh>adb shell
* daemon not running. starting it now on port 5037 *
* daemon started successfully *
$ su
su
# echo 1 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online
# echo performance > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
echo performance > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
# echo performance > /sys/devices/system/cpu/cpu1/cpufreq/scaling_governor
echo performance > /sys/devices/system/cpu/cpu1/cpufreq/scaling_governor
# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
[B]501035[/B]
# cat /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq
cat /sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_cur_freq
[B]501035[/B]
even if i raise min freq to 1000 it reach 501 only
if i run tegrastats -max
i see both cores running and it's the same...
both cores are running max at 501mhz
i posted about this in the overclock thread that has been closed, but then i received many pm about the same issue from many other users...
so this is not only my case, and mostly we come from recovering the psd (mmcblk0p3) partition that was wiped by tenfar's recovery (the option to partition the internal sd card)
now i know that psd partition is not flashed from a stock rom and contains valuable hardware data configuration files.
most of us used the mmcblk0p3.img dump found in the github to restore the partition...
did we miss a step recovering? we are all users, we made till this point, we need a dev...anyone out there?
Click to expand...
Click to collapse

---

KeRmiT80 said:
even if i raise min freq to 1000 it reach 501 only
if i run tegrastats -max
i see both cores running and it's the same...
both cores are running max at 501mhz
i posted about this in the overclock thread that has been closed, but then i received many pm about the same issue from many other users...
so this is not only my case, and mostly we come from recovering the psd (mmcblk0p3) partition that was wiped by tenfar's recovery (the option to partition the internal sd card)
now i know that psd partition is not flashed from a stock rom and contains valuable hardware data configuration files.
most of us used the mmcblk0p3.img dump found in the github to restore the partition...
did we miss a step recovering? we are all users, we made till this point, we need a dev...anyone out there?
Click to expand...
Click to collapse
Unless the phone is on heavy load you'll only get idle speeds, an idle speed of 501Mhz still seems pretty high though, I would be expecting around 300Mhz per core...
But there is a command-set to lock the frequency, will post once I find it....
Cheers

---

no it's not idle speed,
i set governor to performance and set max and min to 1000mhz, but it reaches only 501, even using tegrastats -max command (max cpu load)
and offcourse as all the other users we score half of the points in all benchmarks and loading times are doubled...
these are old...
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edit: if i set lower values the scaling works fine, but every value above 501 is not applied.

---

Well it's kinda obvious, you need to flash a retail /pds partition. The thing is, you wont get it, cuz it has sensitive data like IMEI, MAC address, serial number, etc.

---

i mostly replaced the partition with the dump, only could change mac address and bt. but my imei or serial still the same...
anyway at least for me is not kinda obvious...how exactly datas like imei or serial should affect my cpu frequencies?
wouldn't be that, same as for imei or serial, the dump did not contain certain data?
maybe we're just missing a file, maybe some expecific for tegra devices that overrides froyo's cpu governor/scaling/frequencies...
just supposing

---

weird, the serial number of the device is in the /pds/factory/fti file. the Bt mac address is under /pds/bt/bt_bdaddr and the wifi mac address is /pds/wifi/wlan_mac.bin , there are several other files for which i dont know exactly what they are (i guess the camera settings dont affect your governor) ...

---

Moved to proper forum.

---

crnkoj said:
weird, the serial number of the device is in the /pds/factory/fti file. the Bt mac address is under /pds/bt/bt_bdaddr and the wifi mac address is /pds/wifi/wlan_mac.bin , there are several other files for which i dont know exactly what they are (i guess the camera settings dont affect your governor) ...
Click to expand...
Click to collapse
Those are exactly the files we edited to keep our mac address, bt etc.
The rest as far as I know there are some hardware configs, screen buttons, sensors...but don t know if we are looking in the correct place
Unfortunately we've been moved in a section none could help will read anymore...

---

Man my shows 1000mhz. And my score on quadrante is 2840 with stock at&t moto
Sent from my MB860 using XDA App

---

EclipseX said:
Man my shows 1000mhz. And my score on quadrante is 2840 with stock at&t moto
Sent from my MB860 using XDA App
Click to expand...
Click to collapse
that's the idea...

---

so... there is no dev around here that knows where is our "bios" or how to configure to set the correct default frequency??? possible??
it's not an overclock module, we need to restore the very basic hardware cpu configuration...i think (correct me if i'm wrong) that has nothing to do with sensitive datas
shouldnt be so hard as trying to crack the bootloader...

---

i still trying to see what's wrong
these are 2 outputs for your consideration
Code:
# cat /proc/mtd
dev: size erasesize name
(nothing mounted? )
Code:
# cat /sys/devices/system/cpu/cpu0/cpufreq/vdd_levels_havs
/sys/devices/system/cpu/cpu0/cpufreq/vdd_levels_havs: No such file or directory
(clock speeds, voltages?)

---

i found this file around tegra cpu driver
cpu-tegra.c
Code:
/*
* arch/arm/mach-tegra/cpu-tegra.c
*
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Colin Cross <[email protected]>
* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/system.h>
#include <mach/hardware.h>
#include <mach/clk.h>
/* Frequency table index must be sequential starting at 0 */
static struct cpufreq_frequency_table freq_table[] = {
{ 0, 312000 },
{ 1, 456000 },
{ 2, 608000 },
{ 3, 760000 },
{ 4, 816000 },
{ 5, 912000 },
{ 6, 1000000 },
{ 7, CPUFREQ_TABLE_END },
};
#define NUM_CPUS 2
static struct clk *cpu_clk;
static unsigned long target_cpu_speed[NUM_CPUS];
int tegra_verify_speed(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, freq_table);
}
unsigned int tegra_getspeed(unsigned int cpu)
{
unsigned long rate;
if (cpu >= NUM_CPUS)
return 0;
rate = clk_get_rate(cpu_clk) / 1000;
return rate;
}
static int tegra_update_cpu_speed(void)
{
int i;
unsigned long rate = 0;
int ret = 0;
struct cpufreq_freqs freqs;
for_each_online_cpu(i)
rate = max(rate, target_cpu_speed[i]);
freqs.old = tegra_getspeed(0);
freqs.new = rate;
if (freqs.old == freqs.new)
return ret;
for_each_online_cpu(freqs.cpu)
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
#ifdef CONFIG_CPU_FREQ_DEBUG
printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
freqs.old, freqs.new);
#endif
ret = clk_set_rate_cansleep(cpu_clk, freqs.new * 1000);
if (ret) {
pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
freqs.new);
return ret;
}
for_each_online_cpu(freqs.cpu)
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
return 0;
}
static int tegra_target(struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
int idx;
unsigned int freq;
cpufreq_frequency_table_target(policy, freq_table, target_freq,
relation, &idx);
freq = freq_table[idx].frequency;
target_cpu_speed[policy->cpu] = freq;
return tegra_update_cpu_speed();
}
static int tegra_cpu_init(struct cpufreq_policy *policy)
{
if (policy->cpu >= NUM_CPUS)
return -EINVAL;
cpu_clk = clk_get_sys(NULL, "cpu");
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
cpufreq_frequency_table_cpuinfo(policy, freq_table);
cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
policy->cur = tegra_getspeed(policy->cpu);
target_cpu_speed[policy->cpu] = policy->cur;
/* FIXME: what's the actual transition time? */
policy->cpuinfo.transition_latency = 300 * 1000;
policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
cpumask_copy(policy->related_cpus, cpu_possible_mask);
return 0;
}
static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
cpufreq_frequency_table_cpuinfo(policy, freq_table);
clk_put(cpu_clk);
return 0;
}
static struct freq_attr *tegra_cpufreq_attr[] = {
&cpufreq_freq_attr_scaling_available_freqs,
NULL,
};
static struct cpufreq_driver tegra_cpufreq_driver = {
.verify = tegra_verify_speed,
.target = tegra_target,
.get = tegra_getspeed,
.init = tegra_cpu_init,
.exit = tegra_cpu_exit,
.name = "tegra",
.attr = tegra_cpufreq_attr,
};
static int __init tegra_cpufreq_init(void)
{
return cpufreq_register_driver(&tegra_cpufreq_driver);
}
static void __exit tegra_cpufreq_exit(void)
{
cpufreq_unregister_driver(&tegra_cpufreq_driver);
}
MODULE_AUTHOR("Colin Cross <[email protected]>");
MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
it contains the drivers to set cpu frequencies and scaling...
i suppose that we should find somewhere a module based on this, where?
how to use?

---

800 visits and none with the knowledge/will to answer?
we just need the original stock frequencies to be loaded and running not needed an overclock module or something different from that our stock phones should have already (for the moment ) .
or at least a technical explanation of why our phones are irremediably screwed and cannot run higher cpu frequencies but 216-501 mhz range...
didn't think was harder that unlocking the bootloader

---

dmesg partial output (full as attachment)
my senses tell me that the part below is about the cpu and if you can see seema it starts itself correctly
Code:
[ 13.819798] Calibrating delay loop... 1992.29 BogoMIPS (lpj=9961472)
[ 14.089778] Security Framework initialized
[ 14.089798] TOMOYO Linux initialized
[ 14.089849] Mount-cache hash table entries: 512
[ 14.090279] Initializing cgroup subsys cpuacct
[ 14.090301] Initializing cgroup subsys devices
[ 14.090310] Initializing cgroup subsys freezer
[ 14.090336] CPU: Testing write buffer coherency: ok
[ 14.090539] Calibrating local timer... 1.19MHz.
[ 14.199862] CPU1: Booted secondary processor
[ 14.469653] Brought up 2 CPUs
[ 14.469668] SMP: Total of 2 processors activated (3984.58 BogoMIPS).
[ 14.469689] CPU0 attaching sched-domain:
[ 14.469699] domain 0: span 0-1 level CPU
[ 14.469708] groups: 0 1
[ 14.469726] CPU1 attaching sched-domain:
[ 14.469734] domain 0: span 0-1 level CPU
[ 14.469742] groups: 1 0
[ 14.493421] regulator: core version 0.5
[ 14.493841] NET: Registered protocol family 16
[ 14.497644] Chip Id: 0x20 (Handheld SOC) Major: 0x1 Minor: 0x3 SKU: 0xf
[ 14.498246] NVRM Got shmoo boot argument (at 0xea838004)
[ 14.498257] NVRM corner (2, 1)
[ 14.498469] NVRM CLOCKS: PLLX0: 1000000 Khz
[ 14.498478] NVRM CLOCKS: PLLM0: 600000 Khz
[ 14.498485] NVRM CLOCKS: PLLC0: 600000 Khz
[ 14.498491] NVRM CLOCKS: PLLP0: 216000 Khz
[ 14.498497] NVRM CLOCKS: PLLA0: 11289 Khz
[ 14.498503] NVRM CLOCKS: CPU: 1000000 Khz
[ 14.498509] NVRM CLOCKS: AVP: 240000 Khz
[ 14.498515] NVRM CLOCKS: System Bus: 240000 Khz
[ 14.498522] NVRM CLOCKS: Memory Controller: 300000
[ 14.498530] NVRM CLOCKS: External Memory Controller: 600000
[ 14.499072] Local timer scaling factor 2097, shift 24
[ 14.499107] PL310/L2C-310 cache controller enabled
[ 14.860001] tegra_setup_spi: registering SPI slave tegra_spi_slave.0
[ 14.861601] Registered reg-fixed-voltage: 0 result: 0
[ 14.862028]
[ 14.862031] mot_setup_lights: 0x740 ES2 display; will enable PWM in LM3532
[ 14.862040]
[ 14.862042] mot_setup_touch: Updating i2c_bus_board_info with correct setup info for TS
[ 14.862063] TOUCH: determining size of the screen
[ 14.862427] mot_wlan_gpio_init Enter
[ 14.863091] tegra_mot_init: registering i2c devices...
[ 14.863099] bus 0: 3 devices
[ 14.863107] bus 3: 2 devices
[ 14.863570] config_unused_pins: ENTRY
[ 14.863619] config_unused_pins: Error (-16) - gpio_reqest failed for unused GPIO 144
[ 14.863630] config_unused_pins: Error (-16) - gpio_reqest failed for unused GPIO 146
[ 14.863645] config_unused_pins: Error (-16) - gpio_reqest failed for unused GPIO 85
[ 14.863683] config_unused_pins: EXIT
[ 14.878317] bio: create slab <bio-0> at 0
[ 14.889703] regulator: sdio_en: 2800 mV
[ 14.890854] SCSI subsystem initialized
[ 14.890904] NvRmSpiOpen() Opening channel Inst 1 and IsMaster 1
[ 14.895169] regulator: sw1: 750 <--> 1100 mV
[ 14.895426] regulator: sw2: 900 <--> 1200 mV
[ 14.895703] regulator: sw3: 1350 <--> 1875 mV
[ 14.895963] regulator: sw4: 900 <--> 1200 mV
[ 14.896291] regulator: sw5: 5050 mV
[ 14.896623] regulator: vusb: 3300 mV
[ 14.896897] regulator: vcam: 2600 <--> 2900 mV
[ 14.898639] regulator: vcsi: 1200 mV
[ 14.898932] regulator: vdac: 1200 <--> 2500 mV
[ 14.899209] regulator: vdig: 1200 <--> 1875 mV
[ 14.899511] regulator: vfuse: 1500 <--> 3150 mV
[ 14.902066] regulator: vhvio: 2775 mV
[ 14.902349] regulator: vsdio: 1500 <--> 3000 mV
[ 14.903128] regulator: vpll: 1800 mV
[ 14.903419] regulator: vrf1: 2500 <--> 2775 mV
[ 14.903692] regulator: vrf2: 2775 mV
[ 14.903969] regulator: vrfref: 2500 <--> 2775 mV
[ 14.904242] regulator: vwlan1: 1800 <--> 1900 mV
[ 14.905599] regulator: vwlan2: 2775 <--> 3300 mV
[ 14.905887] regulator: vsim: 1800 <--> 2900 mV
[ 14.906175] regulator: vsimcard: 1800 <--> 2900 mV
[ 14.906468] regulator: vvib: 1300 <--> 3000 mV
[ 14.907895] regulator: vaudio: 2775 mV normal idle standby
[ 14.908904] ADJUSTED CLOCKS:
[ 14.908914] MC clock is set to 300000 KHz
[ 14.908922] EMC clock is set to 600000 KHz (DDR clock is at 300000 KHz)
[ 14.908930] PLLX0 clock is set to 1000000 KHz
[ 14.908936] PLLC0 clock is set to 600000 KHz
[ 14.908941] CPU clock is set to 1000000 KHz
[ 14.908947] System and AVP clock is set to 240000 KHz
[ 14.908955] GraphicsHost clock is set to 100000 KHz
[ 14.908963] 3D clock is set to 100000 KHz
[ 14.908969] 2D clock is set to 100000 KHz
[ 14.908976] Epp clock is set to 100000 KHz
[ 14.908983] Mpe clock is set to 100000 KHz
[ 14.908989] Vde clock is set to 240000 KHz
[ 14.911169] cpcap_uc cpcap_uc: firmware: using built-in firmware cpcap/firmware_0_2x.fw
[ 15.644201] cpcap_uc cpcap_uc: Loaded HWCFG data:
[ 15.644210] cpcap_uc cpcap_uc: 0x8cfc
[ 15.644216] cpcap_uc cpcap_uc: 0x1009
[ 15.644223] cpcap_uc cpcap_uc: result: 0
[ 15.644291] cpcap_uc cpcap_uc: Started macro 4: 0
[ 15.659289] cpcap_adc cpcap_adc: CPCAP ADC device probed
so i guess something in the os is preventing the cpus to exceed the 501 mhz...
how to debug this?
do you thing is possible to get any answers in this forum?
it is becoming frustrating asking to the wind, should i think atrix section has no developers?

---

I think that is related to some power-saving mechanism. Look at my logcat output with tegrastats -debug
Idle(no program runnig):
Code:
06-22 01:05:38.621 9563 9563 E TegraStats: total0 101 idle0 96 | total1 0 id
le1 0
06-22 01:05:38.629 9563 9563 E TegraStats: DFS CPU load 14, OS CPU load 4
06-22 01:05:38.629 9563 9563 E TegraStats: RAM 433/818MB (lfb 1x1MB) Carveout
29/192MB (lfb 93MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB)
GART_Non-Pins(48KB, lnpb(48KB)) IRAM 0/256kB (lfb 256kB) | DFS(%@MHz): [B]cpu [4%,
off]@300[/B] avp 2%@100 vde 0%@171 emc 0%@108
06-22 01:05:39.630 9563 9563 E TegraStats: total0 101 idle0 98 | total1 0 id
le1 0
06-22 01:05:39.630 9563 9563 E TegraStats: DFS CPU load 15, OS CPU load 2
06-22 01:05:39.630 9563 9563 E TegraStats: RAM 433/818MB (lfb 1x1MB) Carveout
29/192MB (lfb 93MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB)
GART_Non-Pins(48KB, lnpb(48KB)) IRAM 0/256kB (lfb 256kB) | DFS(%@MHz): [B]cpu [2%,
off]@300[/B] avp 2%@100 vde 0%@171 emc 0%@108
With heavy load (Stability test runnig)
Code:
06-22 01:06:22.402 1432 2058 I : odm_disp_esd_thread is running(67) st
ate=1
06-22 01:06:22.582 9606 9606 D dalvikvm: GC_FOR_MALLOC freed 2602 objects / 51
4416 bytes in 37ms
06-22 01:06:22.692 2013 2038 D StatusBarPolicy: mSignalStrength=SignalStrength
: 15 -1 -1 -1 -1 -1 -1 gsm 3 -83 -255
06-22 01:06:22.692 2013 2038 D StatusBarPolicy: raw_sig_level=-83,raw_ecno_ber
=-255,raw_rat=3
06-22 01:06:22.692 2013 2038 D StatusBarPolicy: iconLevel = 4
06-22 01:06:22.912 9800 9800 E TegraStats: total0 101 idle0 1 | total1 101 i
dle1 0
06-22 01:06:22.912 9800 9800 E TegraStats: DFS CPU load 100, OS CPU load 99
06-22 01:06:22.912 9800 9800 E TegraStats: RAM 443/818MB (lfb 1x1MB) Carveout
21/192MB (lfb 93MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB)
GART_Non-Pins(48KB, lnpb(48KB)) IRAM 0/256kB (lfb 256kB) | DFS(%@MHz): [B]cpu [99%
,100%]@1000[/B] avp 2%@100 vde 0%@171 emc 43%@300
06-22 01:06:23.909 9800 9800 E TegraStats: total0 100 idle0 0 | total1 100 i
dle1 2
06-22 01:06:23.919 9800 9800 E TegraStats: DFS CPU load 100, OS CPU load 99
06-22 01:06:23.919 9800 9800 E TegraStats: RAM 443/818MB (lfb 1x1MB) Carveout
21/192MB (lfb 93MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB)
GART_Non-Pins(48KB, lnpb(48KB)) IRAM 0/256kB (lfb 256kB) | DFS(%@MHz): [B]cpu [100
%,98%]@1000[/B] avp 2%@100 vde 0%@171 emc 42%@300
Look at bolded stats
Da_G said:
Hi again
cpu [X%,Y%]@Z - X is the percent of CPU0 being used relative to the current running frequency Z. Y is the percent of CPU1 being used (or 'off' if second core is turned off.) Z is the CPU frequency in MHz (the frequency will dynamically go up or down depending on what workload the CPU is seeing.)
Click to expand...
Click to collapse
I have installed Recovery on my Atrix, so it shouldn't have any effect on cpu freq etc.

---

yes i posted this in the other thread...
KeRmiT80 said:
i run the stats while doing the setcpu stress test, tegrastats -max
both cores were running at 100%@501 mhz
shouldn't run at 1 ghz each core?
why in set cpu i get only 501mhz and my cpu benchmarks scores are half than before?
Code:
RT_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 9%@300
06-21 15:51:42.402 12552 12552 E TegraStats: RAM 365/818MB (lfb 14x4MB) Carveout 25/192MB (lfb 119MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB) GART_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 9%@300
06-21 15:51:42.512 1419 2430 I : odm_disp_esd_thread is running(96) state=1
06-21 15:51:43.402 12552 12552 E TegraStats: RAM 365/818MB (lfb 14x4MB) Carveout 25/192MB (lfb 119MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB) GART_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 8%@300
06-21 15:51:44.402 12552 12552 E TegraStats: RAM 365/818MB (lfb 14x4MB) Carveout 25/192MB (lfb 119MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB) GART_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 9%@300
06-21 15:51:45.412 12552 12552 E TegraStats: RAM 365/818MB (lfb 14x4MB) Carveout 25/192MB (lfb 119MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB) GART_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 9%@300
06-21 15:51:45.882 5171 5171 D dalvikvm: GC_EXPLICIT freed 2692 objects / 188120 bytes in 128ms
06-21 15:51:46.412 12552 12552 E TegraStats: RAM 365/818MB (lfb 14x4MB) Carveout 25/192MB (lfb 119MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB) GART_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 9%@300
06-21 15:51:47.422 12552 12552 E TegraStats: RAM 365/818MB (lfb 14x4MB) Carveout 25/192MB (lfb 119MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB) GART_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 9%@300
06-21 15:51:48.422 12552 12552 E TegraStats: RAM 365/818MB (lfb 14x4MB) Carveout 25/192MB (lfb 119MB) GART 48/32768KB (lfb 32MB) GART_Free(32720KB) GART_Pins(0KB) GART_Non-Pins(48KB, lnpb(48KB)) IRAM 124/256kB (lfb 132kB) | DFS(%@MHz): cpu [100%,100%]@501 avp 2%@240 vde 0%@240 emc 9%@300
Click to expand...
Click to collapse
heavy load max 501 mhz...

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Mine is scaling fine.
Code:
$ cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
300867
$ cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
1000000
Phone was sleeping at 300867 and then I woke it up and it scaled to 1000000.

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mine and the phones of the others that have messed up with tenfar's recovery cannot raise cpu frequencies above 501 mhz even if the initialization seems correct and the max freq is set to 1000mhz.
we can scale from 216 min 300 400 to 501 max
i'm happy to know your phone is working fine...now that i know can you help me with mine?